Conventional static random-access memory (SRAM) devices are generally used in applications requiring high speed, such as, memory in a data processing system, and typically consist of six transistors (6T): two P channel field effect transistors (PFETs) for a pull-up operation, two N channel field effect transistors (NFETs) for pull down, and two NFETs for input/output (i.e. passgate) access. As the size of technology nodes continues to decrease, fin field-effect transistors (FinFETs) are introduced to replace planar transistors, during the fabrication of SRAM devices. As one skilled in the art will understand, the stability of a 6T SRAM cell, in general, is defined by a beta ratio which, for instance, is the ratio of the drive currents of the pull-down transistors to the drive currents of the respective pass-gate transistors.
FIG. 1 illustrates a top plan view of a typical 6T SRAM device 100. In the embodiment illustrated, the SRAM device 100 typically includes one or more regions, for instance, region A and region B. As one skilled in the art will understand, during conventional SRAM fabrication a large number of regions A and B are provided together on a substrate. As depicted, each of these regions A and B include, for instance, two pass-gate transistors 112 that are electrically coupled to two pull-down transistors 110 which, in turn, are electrically coupled to two pull-up transistors 108, respectively. Note that, as illustrated, each of the two pass-gate transistors 112 include two fin structures (referred to hereinafter as “fins”) that allow electrically coupling of one pass-gate transistor 112 to an adjacent pass-gate transistor 112. Additionally, the two fins of the pass-gate transistors 112 also enable electrical coupling of the pass-gate transistor to the neighboring pull-down transistors 110, respectively. Although not depicted in the figures, one skilled in the art will understand that, a source region and a drain region are formed at opposite ends of each of the pass-gate FinFETs 112, pull-down FinFETs 110 and pull-up FinFETs 108.
Continuing with FIG. 1, an equal number of pull-down devices and pass-gate devices provide a tradeoff between the cell size and the cell speed. In this situation, the beta ratio is equal to 1. The unitary beta ratio, for instance, could lead to undesirable issues such as, access disturb. As one skilled in the art will understand, higher beta ratios are desirable to improve the stability of the SRAM cell, without increasing the overall size of the SRAM cell. As understood, regions, for instance, regions A and B, are expanded to form bigger cells which, for instance, are more stable because bigger FET features are relatively more precise.
Enhancements in semiconductor memory device structures and fabrication methods therefor continue to be desired for enhanced performance and commercial advantage.